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Intel invests in next-gen wafers

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Intel has entered into a series of agreements with ASML Holding intended to accelerate the development of 450-millimeter (mm) wafer technology and extreme ultra-violet (EUV) lithography totaling €3,3-billion (about $4,1-billion).

The objective is to shorten the schedule for deploying the lithography equipment supporting these technologies by as much as two years, resulting in significant cost savings and other productivity improvements for semiconductor manufacturers.

To achieve this, Intel is participating in a multi-party development program that includes a cash contribution by Intel to fund relevant ASML research and development (R&D) efforts as well as equity investments in ASML.

The first phase of this programme consists of Intel committing to R&D funding of €553-million (approximately $680-million) to assist ASML in accelerating the development and delivery of 450-mm manufacturing tools, as well as an equity investment of €1,7-billion (approximately $2,1-billion) for approximately 10% of ASML’s pre-transaction issued shares. Intel will record the R&D investment as a combination of R&D expense and pre-payments on future tool deliveries.

The second phase of the programme is conditioned upon ASML shareholder approval. It includes an additional commitment by Intel of R&D funding of €276-million (approximately $340-million) in ASML focused on accelerating EUV, as well as an equity investment of €838 million (approximately $1-billion) for an additional 5% of ASML post-transaction issued shares.

Intel will then hold a total of 15% of ASML’s issued shares. The total equity investment will be €2,5-billion (approximately $3,1-billion). As part of these agreements, Intel is also committing to advanced purchase orders for 450-mm and EUV development and production tools from ASML.

Both phases of the program are subject to standard closing conditions, including customary regulatory approvals. The companies expect both phases of the transaction to close after the shareholder vote in the third quarter.

“Productivity improvements driven by enhanced wafer manufacturing technologies, especially larger silicon wafers and enhanced lithography technologies with EUV are direct enablers of Moore’s Law, which delivers significant economic benefits to consumers,” says Brian Krzanich, Intel senior vice president and chief operating officer. “The transition from one wafer size to the next has historically delivered a 30% to 40% reduction in die cost and we expect the shift from today’s standard 300-mm wafers to larger 450-mm wafers to offer similar benefits. The faster we do this, the sooner we can gain the benefit of productivity improvements, which creates tremendous value for customers and shareholders.”