Intel will start production on its second generation of Penryn processors later this year, keeping its promise of delivering a new process technology with an enhanced microarchitecture or entirely new microarchitecture every year.
The new processors will benefit from enhancements to the Intel Core microarchitecture and also the company's new 45nm process technology with its hafnium-based high-K + metal gate transistor design, which results in higher performance and more energy-efficient processors.
Intel has more than 15 product designes using the 45nm Hi-k technology in various stages of development, and will have two 45nm manufacturing fabs in production by the end of the year, with a total of four by the second half of 2008 that will deliver tens of millions of the processors.
The new roadmap is for six new Penryn processors, including dual and quad-core desktop processors and a dual core mobile processor under the Intel Core processor brand name as well as new dual and quad-core server processors under the Intel Xeon processor brand name.
A processor for higher-end server multiprocessing systems is also under development.
The 45nm next-generation Intel Core2 quad-core processors will have 820-million transistors; the dual-core version has a die size of 107mm2, which is 25% smaller than Intel's current 65nm products and operate at the same or lower power than Intel's current dual core processors.
The mobile Penryn processor has a new advanced power management state called Deep Power Down Technology that reduces the power of the processor during idle periods such that internal transistor power leakage is no longer a factor.
The mobile processor also boasts and enhanced the Intel Dynamic Acceleration Technology available in current Intel Core 2 processors. This feature uses the power headroom freed up when a core is made inactive to boost the performance of another still active core.
Penryn includes Intel Streaming SIMD Extensions 4 (SSE4) instructions, the largest unique instruction set addition since the original SSE Instruction Set Architecture (ISA). This extends the Intel 64 instruction set architecture to expand the performance and capabilities of the Intel Architecture.
The new chips include a number of technical featuers to improve performance, including microprocessor optimisation, enhanced Intel Virtualization technology, higher frequencies, fast division of numbers, larger cachesand a super shuffle engine that allows the chips to perform full-width shuffles in a single cycle.
The next round of product launches, due in 2008, is the Nehalem architecture, which will deliver more performance and energy efficiency gains, adding more performance features and capabilities for new and improved applications.
The Nehalem processors will be dynamically scalable, with dynamically-managed cores, threads, cache, interfaces and power. It will leverage four-instruction issue Intel Core microarchitecture technology and simultaneous multi-threading returns.
They will also include new Intel SSE4 and ATA instruction set architecture additions; multi-level shared cache which leverages Intel Smart Cache technology; leadership system and memory bandwidth; and performance-enhanced dynamic power management.
Nehalem chips will be based on a new system architecture for next-generation Intel processors and platforms, with scalable performance; scalable and configurable system interconnects and integrated memory controllers; and a high-performance integrated graphics engine.