Intel has announced a significant breakthrough in the evolution of the transistor, putting a three-dimensional structure into high-volume manufacturing.
The 3D transistor design called Tri-Gate, first disclosed by Intel in 2002, will be used at the 22-nanometer (nm) node in an Intel chip code-named “Ivy Bridge”.
The three-dimensional Tri-Gate transistors represent a fundamental departure from the two-dimensional planar transistor structure that has powered not only all computers, mobile phones and consumer electronics to-date, but also the electronic controls within cars, spacecraft, household appliances, medical devices and virtually thousands of other everyday devices for decades.
“Intel’s scientists and engineers have once again reinvented the transistor, this time utilising the third dimension,” says Intel President and CEO Paul Otellini. “Amazing, world-shaping devices will be created from this capability as we advance Moore’s Law into new realms.”
Scientists have long recognised the benefits of a 3D structure for sustaining the pace of Moore’s Law as device dimensions become so small that physical laws become barriers to advancement. The key to the latest breakthrough is Intel’s ability to deploy its novel 3D Tri-Gate transistor design into high-volume manufacturing, ushering in the next era of Moore’s Law and opening the door to a new generation of innovations across a broad spectrum of devices.
Moore’s Law is a forecast for the pace of silicon technology development that states that roughly every two years transistor density will double, while increasing functionality and performance and decreasing costs. It has become the basic business model for the semiconductor industry for more than 40 years.
Intel’s 3D Tri-Gate transistors enable chips to operate at lower voltage with lower leakage, providing an unprecedented combination of improved performance and energy efficiency compared to previous transistors. The capabilities give chip designers the flexibility to choose transistors targeted for low power or high performance, depending on the application.
The 22nm 3D Tri-Gate transistors provide up to 37% performance increase at low voltage versus. Intel’s 32nm planar transistors. This incredible gain means that they are ideal for use in small handheld devices, which operate using less energy to “switch” back and forth. Alternatively, the new transistors consume less than half the power when at the same performance as 2D planar transistors on 32nm chips.
“The performance gains and power savings of Intel’s unique 3-D Tri-Gate transistors are like nothing we’ve seen before,” says Mark Bohr, Intel senior fellow. “This milestone is going further than simply keeping up with Moore’s Law. The low-voltage and low-power benefits far exceed what we typically see from one process generation to the next. It will give product designers the flexibility to make current devices smarter and wholly new ones possible. We believe this breakthrough will extend Intel’s lead even further over the rest of the semiconductor industry.”
How it works
Transistors continue to get smaller, cheaper and more energy efficient in accordance with Moore’s Law. Because of this, Intel has been able to innovate and integrate, adding more features and computing cores to each chip, increasing performance, and decreasing manufacturing cost per transistor.
Sustaining the progress of Moore’s Law becomes even more complex with the 22nm generation. Anticipating this, Intel research scientists in 2002 invented what they called a Tri-Gate transistor, named for the three sides of the gate. Today’s announcement follows further years of development in Intel’s highly coordinated research-development-manufacturing pipeline, and marks the implementation of this work for high-volume manufacturing.
The 3-D Tri-Gate transistors are a reinvention of the transistor. The traditional “flat” two-dimensional planar gate is replaced with an incredibly thin three-dimensional silicon fin that rises up vertically from the silicon substrate. Control of current is accomplished by implementing a gate on each of the three sides of the fin – two on each side and one across the top — rather than just one on top, as is the case with the 2D planar transistor. The additional control enables as much transistor current flowing as possible when the transistor is in the “on” state (for performance), and as close to zero as possible when it is in the “off” state (to minimize power), and enables the transistor to switch very quickly between the two states (again, for performance).
Just as skyscrapers let urban planners optimise available space by building upward, Intel’s 3D Tri-Gate transistor structure provides a way to manage density. Since these fins are vertical in nature, transistors can be packed closer together, a critical component to the technological and economic benefits of Moore’s Law. For future generations, designers also have the ability to continue growing the height of the fins to get even more performance and energy-efficiency gains.
“For years we have seen limits to how small transistors can get,” says Moore. “This change in the basic structure is a truly revolutionary approach, and one that should allow Moore’s Law, and the historic pace of innovation, to continue.”
The 3D Tri-Gate transistor will be implemented in the company’s upcoming manufacturing process, called the 22-nm node, in reference to the size of individual transistor features. More than 6-million 22nm Tri-Gate transistors could fit in the period at the end of this sentence.
Intel has demonstrated the world’s first 22nm microprocessor, code-named “Ivy Bridge”, working in a laptop, server and desktop computer. Ivy Bridge-based Intel® Core™ family processors will be the first high-volume chips to use 3-D Tri-Gate transistors. Ivy Bridge is slated for high-volume production readiness by the end of this year.
This silicon technology breakthrough will also aid in the delivery of more highly integrated Intel Atom processor-based products that scale the performance, functionality and software compatibility of Intel architecture while meeting the overall power, cost and size requirements for a range of market segment needs.