Intel has introduced PowerVia, a new approach to delivering power that rethinks how chips are made and how they are tested.
Traditionally computer chips have been built like pizzas – from the bottom up, in layers. In the case of chips, you start with the tiniest features, the transistors, and then you build up increasingly less-tiny layers of wires that connect the transistors and different parts of the chip, called interconnects). Included among those top layers are the wires that bring in the power that makes the chip go.
When the chip is done, it is flipped over, enclosed in packaging that provides connections to the outer world, and its ready to put it in a computer.
Unfortunately, this approach is running into problems. As they get smaller and denser, the layers that share interconnects and power connections have become an increasingly chaotic web that hinders the overall performance of each chip.
Once an afterthought, “now they have a huge impact,” says Ben Sell, vice-president of technology development at Intel and part of the team that brought PowerVia to fruition. In short, power and signals fade, requiring workarounds or simply dumping more power in.
That’s not to say Intel teams didn’t foresee these issues — research and development on a new approach dates back a decade — nor does Intel face them alone. The solution that Intel and other chipmakers are all working toward is called “backside power”, to find a way to move the power wires below the transistor to the “back” side of the chip and thus leave the interconnect or “front” side cleanly focused only on interconnection.
So why didn’t we always do it this way? Two simple reasons: The old way is more straightforward to make and, as noted, it mostly wasn’t an issue.
Intel’s backside power solution is called PowerVia, and two new papers to be published at the 2023 VLSI Symposium show that Intel has devised a process to manufacture it, test it and demonstrate positive performance results.
For the first time, chipmaking is going two-sided.
Here’s how it works: Transistors are built first, as before, with the interconnect layers added next. Now, flip over the wafer and “polish everything off”, Sell notes, to expose the bottom layer to which the wires for power will be connected.
“We call it silicon technology,” he says. “But the amount of silicon that’s left on these wafers is really tiny.”
After the polish, “now you only have very few metal layers and they’re all very thick”, Sell explains. That leaves “a very direct path for the power delivery to your transistor.”
The benefits of this approach are manifold, Sell confirms, surpassing the added complexity of the new process.
The wires for power, for example, can take up to 20% of that front-side real estate, so with them gone, the interconnect layers can be “relaxed”.
“That more than offsets the cost of this whole big process,” Sell notes, simplifying what had been the most tortuous portion of the manufacturing flow. The net effect is that the two-part flip-it-over process is actually cheaper than the old way.
The benefits aren’t limited to manufacturing. The test chip the Intel team used to prove out the approach — called Blue Sky Creek and based on the Efficient-core (E-core) coming in Intel’s forthcoming Meteor Lake processor for PCs — demonstrated that PowerVia solved both problems caused by the old method. With separated and fatter wires for power and interconnection, “you get better power delivery and you get better signal wiring”, says Sell.
For your average computer user, this means more efficient speed. Get work done faster and with less power, the promise of Moore’s Law delivered again. As the second paper concludes: “The Intel E-core designed with PowerVia demonstrates >5% frequency improvement and >90% cell density with acceptable debug times as Intel 4.”
Sell confirms this is a “substantial” frequency boost for just moving wires around.
The last part of that conclusion — “acceptable debug times” — is a critical achievement alongside the product improvements. Today, chip-testing techniques are based on the accessibility of the transistors in that first and lowest layer. With the transistors now sandwiched in the middle of the chip, “a lot of those techniques had to be redeveloped,” says Sell.
“There were a lot of concerns and hesitancy and that was probably the hardest thing to figure out — how to do debug on this new backside power delivery.” To make things even more challenging, the test chip design team intentionally added some “Easter egg” errors to the chip, unbeknownst to the validation team. The good news? They found the bugs.
“We have made tremendous progress over the last couple of years in developing those debug capabilities and proving them on Blue Sky Creek,” Sell asserts.
That brings up one more novel thing about how Sell and the Intel team figured out the PowerVia recipe. PowerVia will be introduced into Intel-manufactured silicon starting with the Intel 20A node, which enters production in 2024 (Intel 20A will also see the introduction of a new gate-all-around transistor design called RibbonFET; customers of Intel Foundry Services can benefit from both innovations in the subsequent Intel 18A node, arriving later in 2024).
To isolate the development of PowerVia, they took the well-proven transistors from the preceding Intel 4 process node and built a special in-between node with the power and interconnect design planned for Intel 20A.
According to recent reports, Intel’s planned 2024 introduction of PowerVia would put competitors “roughly two years behind” when it comes to backside power.
“At least for this time period,” confirms Sell, “we have a quite competitive backside power delivery option.”
The first opportunity to feel the many benefits of PowerVia will come next year in the form of Arrow Lake, a next-generation Intel processor for PCs built using the Intel 20A process. Its billions of transistors will be inverted, working more efficiently.