AMD’s next-generation AMD EPYC processor, codenamed “Venice”, has become the first HPC product in the industry to be taped out and brought up on the TSMC advanced 2nm (N2) process technology.
This marks a major step forward in the execution of the AMD data centre CPU roadmap, with “Venice” on track to launch next year.
AMD also announced the successful bring up and validation of its 5th Gen AMD EPYC CPU products at TSMC’s new fabrication facility in Arizona.
“TSMC has been a key partner for many years and our deep collaboration with their R&D and manufacturing teams has enabled AMD to consistently deliver leadership products that push the limits of high-performance computing,” says Dr Lisa Su, chair and CEO of AMD.
“Being a lead HPC customer for TSMC’s N2 process and for TSMC Arizona Fab 21 are great examples of how we are working closely together to drive innovation and deliver the advanced technologies that will power the future of computing.”
TSMC chairman and CEO Dr CC Wei comments: “We are proud to have AMD be a lead HPC customer for our advanced 2nm (N2) process technology and TSMC Arizona fab. By working together, we are driving significant technology scaling resulting in better performance, power efficiency and yields for high-performance silicon.
“We look forward to continuing to work closely with AMD to enable the next era of computing.”